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config.h
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1 
2 
8 /*
9  * If this option is enabled, Microsoft ARMASM compatible output is generated
10  * (output file - Cyclone.asm). Otherwise GNU as syntax is used (Cyclone.s).
11  */
12 #define USE_MS_SYNTAX 0
13 
14 /*
15  * Enable this option if you are going to use Cyclone to emulate Genesis /
16  * Mega Drive system. As VDP chip in these systems had control of the bus,
17  * several instructions were acting differently, for example TAS did'n have
18  * the write-back phase. That will be emulated, if this option is enabled.
19  */
20 #define CYCLONE_FOR_GENESIS 2
21 
22 /*
23  * This option compresses Cyclone's jumptable. Because of this the executable
24  * will be smaller and load slightly faster and less relocations will be needed.
25  * This also fixes the crash problem with 0xfffe and 0xffff opcodes.
26  * Warning: if you enable this, you MUST call CycloneInit() before calling
27  * CycloneRun(), or else it will crash.
28  */
29 #define COMPRESS_JUMPTABLE 1
30 
31 /*
32  * Address mask for memory hadlers. The bits set will be masked out of address
33  * parameter, which is passed to r/w memory handlers.
34  * Using 0xff000000 means that only 24 least significant bits should be used.
35  * Set to 0 if you want to mask unused address bits in the memory handlers yourself.
36  */
37 #define MEMHANDLERS_ADDR_MASK 0
38 
39 /*
40  * Cyclone keeps the 4 least significant bits of SR, PC+membase and it's cycle
41  * counter in ARM registers instead of the context for performance reasons. If you for
42  * any reason need to access them in your memory handlers, enable the options below,
43  * otherwise disable them to improve performance.
44  *
45  * MEMHANDLERS_NEED_PC updates .pc context field with PC value effective at the time
46  * when memhandler was called (opcode address + 2-10 bytes).
47  * MEMHANDLERS_NEED_PREV_PC updates .prev_pc context field to currently executed
48  * opcode address + 2.
49  * Note that .pc and .prev_pc values are always real pointers to memory, so you must
50  * subtract .membase to get M68k PC value.
51  *
52  * Warning: updating PC in memhandlers is dangerous, as Cyclone may internally
53  * increment the PC before fetching the next instruction and continue executing
54  * at wrong location. It's better to wait until Cyclone CycloneRun() finishes.
55  *
56  * Warning: if you enable MEMHANDLERS_CHANGE_CYCLES, you must also enable
57  * MEMHANDLERS_NEED_CYCLES, or else Cyclone will keep reloading the same cycle
58  * count and this will screw timing (if not cause a deadlock).
59  */
60 #define MEMHANDLERS_NEED_PC 0
61 #define MEMHANDLERS_NEED_PREV_PC 0
62 #define MEMHANDLERS_NEED_FLAGS 0
63 #define MEMHANDLERS_NEED_CYCLES 1
64 #define MEMHANDLERS_CHANGE_PC 0
65 #define MEMHANDLERS_CHANGE_FLAGS 0
66 #define MEMHANDLERS_CHANGE_CYCLES 0
67 
68 /*
69  * If the following macro is defined, Cyclone no longer calls read*, write*,
70  * fetch* and checkpc from it's context, it calls these functions directly
71  * instead, prefixed with prefix selected below. For example, if
72  * MEMHANDLERS_DIRECT_PREFIX is set to cyclone_, it will call cyclone_read8
73  * on byte reads.
74  * This is to avoid indirect jumps, which are slower. It also saves one ARM
75  * instruction.
76  */
77 /* MEMHANDLERS_DIRECT_PREFIX "cyclone_" */
78 
79 /*
80  * If enabled, Cyclone will call .IrqCallback routine from it's context whenever it
81  * acknowledges an IRQ. IRQ level (.irq) is not cleared automatically, do this in your
82  * handler if needed.
83  * This function must either return vector number to use for interrupt exception,
84  * CYCLONE_INT_ACK_AUTOVECTOR to use autovector (this is the most common case), or
85  * CYCLONE_INT_ACK_SPURIOUS (least common case).
86  * If disabled, it simply uses appropriate autovector, clears the IRQ level and
87  * continues execution.
88  */
89 #define USE_INT_ACK_CALLBACK 1
90 
91 /*
92  * Enable this if you need old PC, flags or cycles;
93  * or you change cycles in your IrqCallback function.
94  */
95 #define INT_ACK_NEEDS_STUFF 0
96 #define INT_ACK_CHANGES_CYCLES 0
97 
98 /*
99  * If enabled, .ResetCallback is called from the context, whenever RESET opcode is
100  * encountered. All context members are valid and can be changed.
101  * If disabled, RESET opcode acts as an NOP.
102  */
103 #define USE_RESET_CALLBACK 0
104 
105 /*
106  * If enabled, UnrecognizedCallback is called if an invalid opcode is
107  * encountered. All context members are valid and can be changed. The handler
108  * should return zero if you want Cyclone to gererate "Illegal Instruction"
109  * exception after this, or nonzero if not. In the later case you should change
110  * the PC by yourself, or else Cyclone will keep executing that opcode all over
111  * again.
112  * If disabled, "Illegal Instruction" exception is generated and execution is
113  * continued.
114  */
115 #define USE_UNRECOGNIZED_CALLBACK 0
116 
117 /*
118  * This option will also call UnrecognizedCallback for a-line and f-line
119  * (0xa*** and 0xf***) opcodes the same way as described above, only appropriate
120  * exceptions will be generated.
121  */
122 #define USE_AFLINE_CALLBACK 0
123 
124 /*
125  * This makes Cyclone to call checkpc from it's context whenever it changes the PC
126  * by a large value. It takes and should return the PC value in PC+membase form.
127  * The flags and cycle counter are not valid in this function.
128  */
129 #define USE_CHECKPC_CALLBACK 1
130 
131 /*
132  * This determines if checkpc() should be called after jumps when 8 and 16 bit
133  * displacement values were used.
134  */
135 #define USE_CHECKPC_OFFSETBITS_16 1
136 #define USE_CHECKPC_OFFSETBITS_8 0
137 
138 /*
139  * Call checkpc() after DBcc jumps (which use 16bit displacement). Cyclone prior to
140  * 0.0087 never did that.
141  */
142 #define USE_CHECKPC_DBRA 0
143 
144 /*
145  * When this option is enabled Cyclone will do two word writes instead of one
146  * long write when handling MOVE.L or MOVEM.L with pre-decrementing destination,
147  * as described in Bart Trzynadlowski's doc (http://www.trzy.org/files/68knotes.txt).
148  * Enable this if you are emulating a 16 bit system.
149  */
150 #define SPLIT_MOVEL_PD 1
151 
152 /*
153  * Enable emulation of trace mode. Shouldn't cause any performance decrease, so it
154  * should be safe to keep this ON.
155  */
156 #define EMULATE_TRACE 1
157 
158 /*
159  * If enabled, address error exception will be generated if 68k code jumps to an
160  * odd address. Causes very small performance hit (2 ARM instructions for every
161  * emulated jump/return/exception in normal case).
162  * Note: checkpc() must not clear least significant bit of rebased address
163  * for this to work, as checks are performed after calling checkpc().
164  */
165 #define EMULATE_ADDRESS_ERRORS_JUMP 1
166 
167 /*
168  * If enabled, address error exception will be generated if 68k code tries to
169  * access a word or longword at an odd address. The performance cost is also 2 ARM
170  * instructions per access (for address error checks).
171  */
172 #define EMULATE_ADDRESS_ERRORS_IO 0
173 
174 /*
175  * If an address error happens during another address error processing,
176  * the processor halts until it is reset (catastrophic system failure, as the manual
177  * states). This option enables halt emulation.
178  * Note that this might be not desired if it is known that emulated system should
179  * never reach this state.
180  */
181 #define EMULATE_HALT 0
182